Example embodiments relate to a pad interface circuit, and more particularly, to a pad interface circuit having improved reliability in regards to a voltage level of an input voltage source and a method of improving the reliability of the pad interface.
Integrated circuits consisting of semiconductors may include: function blocks performing functions, storage media used by the function blocks, and a central processing unit (CPU) controlling the function blocks. The CPU, the function blocks, and the storage media operate by using an electric source supplied from outside of the integrated circuit. In addition, control signals are supplied from the outside to be used in performing functions of the integrated circuit and signals generated in response to the control signals should be output from the integrated circuit. The signals supplied from the outside, the electric source supplied from the outside, and the signals generated in the integrated circuit are transferred through a pad.
Since the pad may become a path through which undesired electrostatic charges are induced while normal signals and the voltage source supplied from the outside of the integrated circuit are supplied through the pad, an in-out circuit that connects the pad to an internal circuit of the integrated circuit, that is, a pad interface circuit, is designed and implemented to pass the normal signals and to block undesired signals. Therefore, there is a functional difference between the interface circuits disposed between the pad and the integrated circuit when the pad is used as an input unit and as an output unit.
Conventionally, an interface circuit adopting a virtual floating well is used to solve the above problem.
Even when the integrated circuit operates the internal elements by using a supply voltage VDD, a magnitude of the supply voltage Ex_VDD supplied from the outside is generally greater than a voltage level of the supply voltage VDD. For example, when it is assumed that the magnitude of the supply voltage VDD used in the integrated circuit of a wall plug product such as a universal serial bus (USB) is 3.3V (Volts), the magnitude of the supply voltage Ex_VDD, which is applied to the pad of the integrated circuit from the outside, may be 5V. When designing the pad interface circuit of the integrated circuit, the supply voltage Ex_VDD having a higher voltage level should not affect a gate oxide layer of the interface circuit.
When the supply voltage VDD of the integrated circuit is supplied to the pad interface circuit, the functions of the pad interface circuit can be executed. However, when the voltage source VDD is not supplied to the pad interface circuit, the supply voltage Ex_VDD supplied from the outside may affect the gate oxide layers of the transistors forming the interface circuit due to structural characteristics of the interface circuit, and accordingly, lifespan of the pad interface circuit may be reduced and reliability of the pad interface circuit may be degraded.